| Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET N Loubet, T Hook, P Montanini, CW Yeung, S Kanakasabapathy, ... 2017 symposium on VLSI technology, T230-T231, 2017 | 867 | 2017 |
| Chip to wiring interface with single metal alloy layer applied to surface of copper interconnect CJ Sambucetti, X Chen, SC Seo, BN Agarwala, CK Hu, NE Lustig, ... US Patent 6,573,606, 2003 | 307 | 2003 |
| A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ... 2016 IEEE international electron devices meeting (IEDM), 2.7. 1-2.7. 4, 2016 | 186 | 2016 |
| Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications K Cheng, A Khakifirooz, P Kulkarni, S Ponoth, J Kuss, D Shahrjerdi, ... 2009 IEEE international electron devices meeting (IEDM), 1-4, 2009 | 174 | 2009 |
| Tantalum nitride films grown by inorganic low temperature thermal chemical vapor deposition diffusion barrier properties in copper metallization AE Kaloyeros, X Chen, T Stark, K Kumar, SC Seo, GG Peterson, HL Frisch, ... Journal of the electrochemical society 146 (1), 170, 1999 | 115 | 1999 |
| A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI KI Seo, B Haran, D Gupta, D Guo, T Standaert, R Xie, H Shang, E Alptekin, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 110 | 2014 |
| Fully depleted extremely thin SOI technology fabricated by a novel integration scheme featuring implant-free, zero-silicon-loss, and faceted raised source/drain K Cheng, A Khakifirooz, P Kulkarni, S Kanakasabapathy, S Schmitz, ... 2009 Symposium on VLSI Technology, 212-213, 2009 | 97 | 2009 |
| 22 nm technology compatible fully functional 0.1 μm26T-SRAM cell BS Haran, A Kumar, L Adam, J Chang, V Basker, S Kanakasabapathy, ... 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 96 | 2008 |
| Effects of overlayers on electromigration reliability improvement for cu/low k interconnects CK Hu, D Canaperi, ST Chen, LM Gignac, B Herbst, S Kaldor, M Krishnan, ... 2004 IEEE International Reliability Physics Symposium. Proceedings, 222-228, 2004 | 75 | 2004 |
| Atom motion of Cu and Co in Cu damascene lines with a CoWP cap CK Hu, LM Gignac, R Rosenberg, B Herbst, S Smith, J Rubino, ... Applied physics letters 84 (24), 4986-4988, 2004 | 67 | 2004 |
| A high performance 0.13/spl mu/m copper BEOL technology with low-k dielectric RD Goldblatt, B Agarwala, MB Anand, EP Barth, GA Biery, ZG Chen, ... Proceedings of the IEEE 2000 International Interconnect Technology …, 2000 | 66 | 2000 |
| Effect of substrate bias on the properties of diamondlike carbon films deposited using unbalanced magnetron sputtering SC Seo, DC Ingram, HH Richardson Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 13 (6 …, 1995 | 63 | 1995 |
| Process to increase reliability CuBEOL structures X Chen, M Krishnan, JM Rubino, CJ Sambucetti, SC Seo, JA Tornello US Patent 6,503,834, 2003 | 53 | 2003 |
| Superfilled metal contact vias for semiconductor devices JJ Kelly, VS Basker, BS Haran, SC Seo, TA Vo US Patent 8,691,687, 2014 | 51 | 2014 |
| MOSFET gate and source/drain contact metallization SC Seo, BB Doris, CC Yang US Patent 8,551,874, 2013 | 47 | 2013 |
| ETSOI CMOS for system-on-chip applications featuring 22nm gate length, sub-100nm gate pitch, and 0.08µm2 SRAM cell K Cheng, A Khakifirooz, P Kulkarni, S Ponoth, B Haran, A Kumar, T Adam, ... 2011 Symposium on VLSI Technology-Digest of Technical Papers, 128-129, 2011 | 46 | 2011 |
| Electromigration Cu mass flow in Cu interconnections CK Hu, D Canaperi, ST Chen, LM Gignac, S Kaldor, M Krishnan, ... Thin Solid Films 504 (1-2), 274-278, 2006 | 44 | 2006 |
| Extremely thin SOI (ETSOI) technology: Past, present, and future K Cheng, A Khakifirooz, P Kulkarni, S Ponoth, J Kuss, LF Edge, A Kimball, ... 2010 IEEE International SOI Conference (SOI), 1-4, 2010 | 43 | 2010 |
| Challenges and opportunities of extremely thin SOI (ETSOI) CMOS technology for future low power and general purpose system-on-chip applications A Khakifirooz, K Cheng, P Kulkarni, J Cai, S Ponoth, J Kuss, BS Haran, ... Proceedings of 2010 International Symposium on VLSI Technology, System and …, 2010 | 37 | 2010 |
| Nanowire FET including nanowire channel spacers SC Seo US Patent 10,236,362, 2019 | 36 | 2019 |
