| Maximizing multiprocessor performance with the SUIF compiler MW Hall, JM Anderson, SP Amarasinghe, BR Murphy, SW Liao, ... Computer 29 (12), 84-89, 1996 | 828 | 1996 |
| SUIF: An infrastructure for research on parallelizing and optimizing compilers RP Wilson, RS French, CS Wilson, SP Amarasinghe, JM Anderson, ... ACM Sigplan Notices 29 (12), 31-37, 1994 | 777 | 1994 |
| The architecture of the DIVA processing-in-memory chip J Draper, J Chame, M Hall, C Steele, T Barrett, J LaCoss, J Granacki, ... Proceedings of the 16th international conference on Supercomputing, 14-25, 2002 | 345 | 2002 |
| A scalable auto-tuning framework for compiler optimization A Tiwari, C Chen, J Chame, M Hall, JK Hollingsworth 2009 IEEE International Symposium on Parallel & Distributed Processing, 1-12, 2009 | 303 | 2009 |
| CHiLL: A framework for composing high-level loop transformations C Chen, J Chame, M Hall Technical Report 08-897, University of Southern California, 2008 | 295 | 2008 |
| Mapping irregular applications to DIVA, a PIM-based data-intensive architecture M Hall, P Kogge, J Koller, P Diniz, J Chame, J Draper, J LaCoss, ... Proceedings of the 1999 ACM/IEEE Conference on Supercomputing, 57-es, 1999 | 282 | 1999 |
| Detecting coarse-grain parallelism using an interprocedural parallelizing compiler MH Hall, SP Amarasinghe, BR Murphy, SW Liao, MS Lam Proceedings of the 1995 ACM/IEEE conference on Supercomputing, 49-es, 1995 | 223 | 1995 |
| Superword-level parallelism in the presence of control flow J Shin, M Hall, J Chame International Symposium on Code Generation and Optimization, 165-175, 2005 | 173 | 2005 |
| A methodology for procedure cloning KD Cooper, MW Hall, K Kennedy Computer Languages 19 (2), 105-117, 1993 | 171 | 1993 |
| Combining models and guided empirical search to optimize for multiple levels of the memory hierarchy C Chen, J Chame, M Hall International Symposium on Code Generation and Optimization, 111-122, 2005 | 167 | 2005 |
| A compiler approach to fast hardware design space exploration in FPGA-based systems B So, MW Hall, PC Diniz ACM SIGPLAN Notices 37 (5), 165-176, 2002 | 165 | 2002 |
| The ParaScope parallel programming environment KD Cooper, MW Hall, RT Hood, K Kennedy, KS McKinley, ... Proceedings of the IEEE 81 (2), 244-263, 1993 | 157 | 1993 |
| Procedure cloning KD Cooper, MW Hall, K Kennedy Proceedings of the 1992 International Conference on Computer Languages, 96 …, 1992 | 151 | 1992 |
| Autotuning in high-performance computing applications P Balaprakash, J Dongarra, T Gamblin, M Hall, JK Hollingsworth, B Norris, ... Proceedings of the IEEE 106 (11), 2068-2083, 2018 | 150 | 2018 |
| Exascale software study: Software challenges in extreme scale systems S Amarasinghe, D Campbell, W Carlson, A Chien, W Dally, E Elnohazy, ... DARPA IPTO, September, 2009 | 147 | 2009 |
| Roofline model toolkit: A practical tool for architectural and program analysis YJ Lo, S Williams, B Van Straalen, TJ Ligocki, MJ Cordery, NJ Wright, ... High Performance Computing Systems. Performance Modeling, Benchmarking, and …, 2015 | 145 | 2015 |
| Managing interprocedural optimization MW Hall Rice University, 1991 | 138 | 1991 |
| Loop transformation recipes for code generation and auto-tuning M Hall, J Chame, C Chen, J Shin, G Rudy, MM Khan International Workshop on Languages and Compilers for Parallel Computing, 50-64, 2009 | 137 | 2009 |
| An experiment with inline substitution KD Cooper, MW Hall, L Torczon Software: Practice and Experience 21 (6), 581-601, 1991 | 133 | 1991 |
| Loop and data transformations for sparse matrix code A Venkat, M Hall, M Strout ACM SIGPLAN Notices 50 (6), 521-532, 2015 | 126 | 2015 |
