| VARIUS: A model of process variation and resulting timing errors for microarchitects SR Sarangi, B Greskamp, R Teodorescu, J Nakano, A Tiwari, J Torrellas IEEE Transactions on Semiconductor Manufacturing 21 (1), 3-13, 2008 | 533 | 2008 |
| Variation-aware application scheduling and power management for chip multiprocessors R Teodorescu, J Torrellas ACM SIGARCH computer architecture news 36 (3), 363-374, 2008 | 450 | 2008 |
| One bit flips, one cloud flops:{Cross-VM} row hammer attacks and privilege escalation Y Xiao, X Zhang, Y Zhang, R Teodorescu 25th USENIX security symposium (USENIX Security 16), 19-35, 2016 | 321 | 2016 |
| Caching with selective multicasting in a publish-subscribe network S Yajnik, TW Chen, PF Yang, R Teodorescu US Patent 7,672,275, 2010 | 254 | 2010 |
| HARD: Hardware-assisted lockset-based race detection P Zhou, R Teodorescu, Y Zhou 2007 IEEE 13th International Symposium on High Performance Computer …, 2007 | 197 | 2007 |
| Accident risk prediction based on heterogeneous sparse data: New dataset and insights S Moosavi, MH Samavatian, S Parthasarathy, R Teodorescu, R Ramnath Proceedings of the 27th ACM SIGSPATIAL international conference on advances …, 2019 | 160 | 2019 |
| Mitigating parameter variation with dynamic fine-grain body biasing R Teodorescu, J Nakano, A Tiwari, J Torrellas 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2007 | 141 | 2007 |
| Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors A Bacha, R Teodorescu Proceedings of the 40th annual international symposium on computer …, 2013 | 111 | 2013 |
| Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips TN Miller, X Pan, R Thomas, N Sedaghati, R Teodorescu IEEE International Symposium on High-Performance Comp Architecture, 1-12, 2012 | 104 | 2012 |
| Adaptive parallel execution of deep neural networks on heterogeneous edge devices L Zhou, MH Samavatian, A Bacha, S Majumdar, R Teodorescu Proceedings of the 4th ACM/IEEE Symposium on Edge Computing, 195-208, 2019 | 103 | 2019 |
| Specshield: Shielding speculative data from microarchitectural covert channels K Barber, A Bacha, L Zhou, Y Zhang, R Teodorescu 2019 28th International Conference on Parallel Architectures and Compilation …, 2019 | 98 | 2019 |
| Distributing deep neural networks with containerized partitions at the edge L Zhou, H Wen, R Teodorescu, DHC Du 2nd USENIX Workshop on Hot Topics in Edge Computing (HotEdge 19), 2019 | 96 | 2019 |
| Log-based architectures for general-purpose monitoring of deployed code S Chen, B Falsafi, PB Gibbons, M Kozuch, TC Mowry, R Teodorescu, ... Proceedings of the 1st workshop on Architectural and system support for …, 2006 | 95 | 2006 |
| Using ECC feedback to guide voltage speculation in low-voltage processors A Bacha, R Teodorescu 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture, 306-318, 2014 | 77 | 2014 |
| VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors TN Miller, R Thomas, X Pan, R Teodorescu ACM SIGARCH Computer Architecture News 40 (3), 249-260, 2012 | 77 | 2012 |
| SPEECHMINER: A framework for investigating and measuring speculative execution vulnerabilities Y Xiao, Y Zhang, R Teodorescu arXiv preprint arXiv:1912.00329, 2019 | 57 | 2019 |
| Parichute: Generalized turbocode-based error correction for near-threshold caches TN Miller, R Thomas, J Dinan, B Adcock, R Teodorescu 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 351-362, 2010 | 55 | 2010 |
| A systematic look at ciphertext side channels on AMD SEV-SNP M Li, L Wilke, J Wichelmann, T Eisenbarth, R Teodorescu, Y Zhang 2022 IEEE Symposium on Security and Privacy (SP), 337-351, 2022 | 48 | 2022 |
| Authenticache: Harnessing cache ECC for system authentication A Bacha, R Teodorescu Proceedings of the 48th International Symposium on Microarchitecture, 128-140, 2015 | 43 | 2015 |
| SWICH: A prototype for efficient cache-level checkpointing and rollback R Teodorescu, J Nakano, J Torrellas IEEE Micro 26 (5), 28-40, 2006 | 37 | 2006 |
