Siddharth Joshi
Siddharth Joshi
Assistant Professor at University of Notre Dame, Dept. of Comp. Science and Eng. and Dept. of
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Zitiert von
Zitiert von
A compute-in-memory chip based on resistive random-access memory
W Wan, R Kubendran, C Schaefer, SB Eryilmaz, W Zhang, D Wu, S Deiss, ...
Nature 608 (7923), 504-512, 2022
Ferroelectric ternary content-addressable memory for one-shot learning (vol 35, pg 258, 2019)
K Ni, X Yin, AF Laguna, S Joshi, S Dunkel, M Trentzsch, J Mueller, ...
NATURE ELECTRONICS 3 (2), 130-130, 2020
Stochastic synapses enable efficient brain-inspired learning machines
EO Neftci, BU Pedroni, S Joshi, M Al-Shedivat, G Cauwenberghs
Frontiers in neuroscience 10, 241, 2016
Memristor for computing: Myth or reality?
S Hamdioui, S Kvatinsky, G Cauwenberghs, L Xie, N Wald, S Joshi, ...
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017
Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems
GC Jongkil Park, Theodore Yu, Siddharth Joshi, Christoph Maier
IEEE Transactions on Neural Networks and Learning Systems, 2016
33.1 A 74 TMACS/W CMOS-RRAM neurosynaptic core with dynamically reconfigurable dataflow and in-situ transposable weights for probabilistic graphical models
W Wan, R Kubendran, SB Eryilmaz, W Zhang, Y Liao, D Wu, S Deiss, ...
2020 IEEE International Solid-State Circuits Conference-(ISSCC), 498-500, 2020
Head Harness &Wireless EEG Monitoring System
P Low, YM Chi, S Joshi, C Uebelher, YA Dubois
US Patent App. 12/913,686, 2011
Sub-Vrms-Noise Sub-W/Channel ADC-Direct Neural Recording With 200-mV/ms Transient Recovery Through Predictive Digital Autoranging
C Kim, S Joshi, H Courellis, J Wang, C Miller, G Cauwenberghs
IEEE Journal of Solid-State Circuits 53 (11), 3101-3110, 2018
FPGA based high performance double-precision matrix multiplication
VBY Kumar, S Joshi, SB Patkar, H Narayanan
International journal of parallel programming 38, 322-338, 2010
Supervised learning in all FeFET-based spiking neural network: Opportunities and challenges
S Dutta, C Schafer, J Gomez, K Ni, S Joshi, S Datta
Frontiers in neuroscience 14, 634, 2020
Dept. of Electr. & Comput. Eng., UC San Diego, La Jolla, CA, USA
T Yu, J Park, S Joshi, C Maier, G Cauwenberghs
Biomedical Circuits and Systems Conference (BioCAS), 2012 IEEE, 21-24, 2012
65k-neuron integrate-and-fire array transceiver with address-event reconfigurable synaptic routing
T Yu, J Park, S Joshi, C Maier, G Cauwenberghs
Biomedical Circuits and Systems Conference (BioCAS), 2012 IEEE, 21-24, 2012
Neuromorphic neural interfaces: from neurophysiological inspiration to biohybrid coupling with nervous systems
FD Broccard, S Joshi, J Wang, G Cauwenberghs
Journal of neural engineering 14 (4), 041002, 2017
Energy Recycling Telemetry IC With Simultaneous 11.5 mW Power and 6.78 Mb/s Backward Data Delivery Over a Single 13.56 MHz Inductive Link
GC Sohmyung Ha, Chul Kim, Jongkil Park, Siddharth Joshi
IEEE Journal of Solid-State Circuits 51 (11), 2664-2678, 2016
Using synchronized oscillators to compute the maximum independent set
A Mallick, MK Bashar, DS Truesdell, BH Calhoun, S Joshi, N Shukla
Nature communications 11 (1), 4689, 2020
Training a Probabilistic Graphical Model With Resistive Switching Electronic Synapses
HSPW Sukru Burc Eryilmaz, Emre Neftci, Siddharth Joshi, SangBum Kim, Matthew ...
IEEE Transactions on Electron Devices 63 (12), 5004-5011, 2016
Scalable event routing in hierarchical neural array architecture with global synaptic connectivity
S Joshi, S Deiss, M Arnold, J Park, T Yu, G Cauwenberghs
2010 12th International Workshop on Cellular Nanoscale Networks and their …, 2010
Experimental demonstration of a reconfigurable coupled oscillator platform to solve the max-cut problem
MK Bashar, A Mallick, DS Truesdell, BH Calhoun, S Joshi, N Shukla
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 6 …, 2020
Neuromorphic architectures with electronic synapses
SB Eryilmaz, S Joshi, E Neftci, W Wan, G Cauwenberghs, HSP Wong
2016 17th International Symposium on Quality Electronic Design (ISQED), 118-123, 2016
A voltage-mode sensing scheme with differential-row weight mapping for energy-efficient RRAM-based in-memory computing
W Wan, R Kubendran, B Gao, S Joshi, P Raina, H Wu, G Cauwenberghs, ...
2020 IEEE Symposium on VLSI Technology, 1-2, 2020
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