Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET N Loubet, T Hook, P Montanini, CW Yeung, S Kanakasabapathy, ... 2017 symposium on VLSI technology, T230-T231, 2017 | 867 | 2017 |
FinFET parasitic capacitance reduction using air gap T Ando, JB Chang, SK Kanakasabapathy, P Kulkarni, TE Standaert, ... US Patent 8,637,384, 2014 | 320 | 2014 |
Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond H Kawasaki, VS Basker, T Yamashita, CH Lin, Y Zhu, J Faltermeier, ... 2009 IEEE international electron devices meeting (IEDM), 1-4, 2009 | 187 | 2009 |
A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ... 2016 IEEE international electron devices meeting (IEDM), 2.7. 1-2.7. 4, 2016 | 186 | 2016 |
FinFET-compatible metal-insulator-metal capacitor WE Haensch, P Kulkarni, T Yamashita US Patent 8,860,107, 2014 | 158 | 2014 |
A 0.063 µm2 FinFET SRAM cell demonstration with conventional lithography using a novel integration scheme with aggressively scaled fin and gate pitch VS Basker, T Standaert, H Kawasaki, CC Yeh, K Maitra, T Yamashita, ... 2010 Symposium on VLSI Technology, 19-20, 2010 | 119 | 2010 |
FinFET parasitic capacitance reduction using air gap T Ando, JB Chang, SK Kanakasabapathy, P Kulkarni, TE Standaert, ... US Patent 8,637,930, 2014 | 118 | 2014 |
Channel doping impact on FinFETs for 22nm and beyond CH Lin, R Kambhampati, RJ Miller, TB Hook, A Bryant, W Haensch, ... 2012 Symposium on VLSI Technology (VLSIT), 15-16, 2012 | 88 | 2012 |
High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell E Leobandung, H Nayakama, D Mocuta, K Miyamoto, M Angyal, HV Meer, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 126-127, 2005 | 85 | 2005 |
Channel geometry impact and narrow sheet effect of stacked nanosheet CW Yeung, J Zhang, R Chao, O Kwon, R Vega, G Tsutsui, X Miao, ... 2018 IEEE international electron devices meeting (IEDM), 28.6. 1-28.6. 4, 2018 | 81 | 2018 |
Air gap spacer formation for nano-scale semiconductor devices K Cheng, TJ Haigh, J Li, EG Liniger, SC Mehta, SV Nguyen, C Park, ... US Patent 10,418,277, 2019 | 78 | 2019 |
Si nanowire CMOS fabricated with minimal deviation from RMG FinFET technology showing record performance I Lauer, N Loubet, SD Kim, JA Ott, S Mignot, R Venigalla, T Yamashita, ... 2015 Symposium on VLSI Technology (VLSI Technology), T140-T141, 2015 | 77 | 2015 |
Sub-25nm FinFET with advanced fin formation and short channel effect engineering T Yamashita, VS Basker, T Standaert, CC Yeh, T Yamamoto, K Maitra, ... 2011 Symposium on VLSI Technology-Digest of Technical Papers, 14-15, 2011 | 76 | 2011 |
Full bottom dielectric isolation to enable stacked nanosheet transistor for low power and high performance applications J Zhang, J Frougier, A Greene, X Miao, L Yu, R Vega, P Montanini, ... 2019 IEEE International Electron Devices Meeting (IEDM), 11.6. 1-11.6. 4, 2019 | 72 | 2019 |
High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL WH Lee, A Waite, H Nii, HM Nayfeh, V McGahay, H Nakayama, D Fried, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 4 …, 2005 | 70 | 2005 |
FINFET technology featuring high mobility SiGe channel for 10nm and beyond D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 66 | 2016 |
Stacked nanowire field effect transistor VS Basker, T Yamashita, CC Yeh US Patent 8,679,902, 2014 | 64 | 2014 |
Bulk fin-field effect transistors with well defined isolation K Cheng, BS Haran, S Ponoth, TE Standaert, T Yamashita US Patent 8,420,459, 2013 | 63 | 2013 |
High-k metal gate fundamental learning and multi-Vt options for stacked nanosheet gate-all-around transistor J Zhang, T Ando, CW Yeung, M Wang, O Kwon, R Galatage, R Chao, ... 2017 IEEE International Electron Devices Meeting (IEDM), 22.1. 1-22.1. 4, 2017 | 62 | 2017 |
Stacked nanosheet field-effect transistor with air gap spacers J Frougier, R Xie, H Zang, K Cheng, T Yamashita, CC Yeh US Patent 10,269,983, 2019 | 61 | 2019 |