V. Narayanan
V. Narayanan
IBM T. J. Watson Research Center
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Zitiert von
Zitiert von
Advanced high-κ dielectric stacks with polySi and metal gates: Recent progress and current challenges
EP Gusev, V Narayanan, MM Frank
IBM Journal of Research and Development 50 (4.5), 387-410, 2006
A comparative study of NBTI and PBTI (charge trapping) in SiO2/HfO2 stacks with FUSI, TiN, Re gates
S Zafar, Y Kim, V Narayanan, C Cabral, V Paruchuri, B Doris, J Stathis, ...
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 23-25, 2006
Switching of ferroelectric polarization in epitaxial BaTiO3 films on silicon without a conducting bottom electrode
C Dubourdieu, J Bruley, TM Arruda, A Posadas, J Jordan-Sweet, ...
Nature nanotechnology 8 (10), 748, 2013
High-/Metal-Gate Fully Depleted SOI CMOS With Single-Silicide Schottky Source/Drain With Sub-30-nm Gate Length
MH Khater, Z Zhang, J Cai, C Lavoie, C D'Emic, Q Yang, B Yang, ...
IEEE Electron Device Letters 31 (4), 275-277, 2010
Oxygen vacancies in high dielectric constant oxide-semiconductor films
S Guha, V Narayanan
Physical review letters 98 (19), 196101, 2007
Ultimate scaling of high-κ gate dielectrics: Higher-κ or interfacial layer scavenging?
T Ando
Materials 5 (3), 478-500, 2012
Comparative study of GaN and AlN nucleation layers and their role in growth of GaN on sapphire by metalorganic chemical vapor deposition
K Lorenz, M Gonsalves, W Kim, V Narayanan, S Mahajan
Applied Physics Letters 77 (21), 3391-3393, 2000
A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
X Chen, S Samavedam, V Narayanan, K Stein, C Hobbs, C Baiocco, W Li, ...
2008 symposium on vlsi technology, 88-89, 2008
Origins of threading dislocations in GaN epitaxial layers grown on sapphire by metalorganic chemical vapor deposition
V Narayanan, K Lorenz, W Kim, S Mahajan
Applied Physics Letters 78 (11), 1544-1546, 2001
A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications
S Krishnan, U Kwon, N Moumen, MW Stoker, ECT Harley, S Bedell, ...
2011 International Electron Devices Meeting, 28.1. 1-28.1. 4, 2011
Fundamental aspects of HfO2-based high-k metal gate stack reliability and implications on tinv-scaling
E Cartier, A Kerber, T Ando, MM Frank, K Choi, S Krishnan, B Linder, ...
2011 International Electron Devices Meeting, 18.4. 1-18.4. 4, 2011
Examination of flatband and threshold voltage tuning of HfO2∕ TiN field effect transistors by dielectric cap layers
S Guha, VK Paruchuri, M Copel, V Narayanan, YY Wang, PE Batson, ...
Applied physics letters 90 (9), 2007
High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing
M Chudzik, B Doris, R Mo, J Sleight, E Cartier, C Dewan, D Park, H Bu, ...
2007 IEEE symposium on VLSI technology, 194-195, 2007
Signal and noise extraction from analog memory elements for neuromorphic computing
N Gong, T Idé, S Kim, I Boybat, A Sebastian, V Narayanan, T Ando
Nature communications 9 (1), 2102, 2018
Understanding mobility mechanisms in extremely scaled HfO2 (EOT 0.42 nm) using remote interfacial layer scavenging technique and Vt-tuning dipoles with gate …
T Ando, MM Frank, K Choi, C Choi, J Bruley, M Hopstaken, M Copel, ...
2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009
Role of oxygen vacancies in V/sub FB//V/sub t/stability of pFET metals on HfO/sub 2
E Cartier, FR McFeely, V Narayanan, P Jamison, BP Linder, M Copel, ...
Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 230-231, 2005
Band-edge high-performance high-k/metal gate n-MOSFETs using cap layers containing group IIA and IIIB elements with gate-first processing for 45 nm and beyond
TC Chen, G Shahidi, S Guha, M Ieong, MP Chudzik, R Jammy, ...
2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 178-179, 2006
High-k/metal gate innovations enabling continued CMOS scaling
MM Frank
2011 Proceedings of the European Solid-State Device Research Conference …, 2011
HERMES Core–A 14nm CMOS and PCM-based In-Memory Compute Core using an array of 300ps/LSB Linearized CCO-based ADCs and local digital processing
R Khaddam-Aljameh, M Stanisavljevic, JF Mas, G Karunaratne, ...
2021 Symposium on VLSI Circuits, 1-2, 2021
Fundamental understanding and optimization of PBTI in nFETs with SiO2/HfO2 gate stack
E Cartier, BP Linder, V Narayanan, VK Paruchuri
2006 International Electron Devices Meeting, 1-4, 2006
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