| A lightweight dataflow approach for design and implementation of SDR systems C Shen, W Plishker, H Wu, SS Bhattacharyya Proceedings of the Wireless Innovation Conference and Product Exposition …, 2010 | 75 | 2010 |
| A model-based schedule representation for heterogeneous mapping of dataflow graphs HH Wu, CC Shen, N Sane, W Plishker, SS Bhattacharyya 2011 IEEE International Symposium on Parallel and Distributed Processing …, 2011 | 25 | 2011 |
| A design tool for efficient mapping of multimedia applications onto heterogeneous platforms CC Shen, HH Wu, N Sane, W Plishker, SS Bhattacharyya 2011 IEEE International Conference on Multimedia and Expo, 1-6, 2011 | 17 | 2011 |
| Design and synthesis for multimedia systems using the targeted dataflow interchange format CC Shen, S Wu, N Sane, HH Wu, W Plishker, SS Bhattacharyya IEEE Transactions on Multimedia 14 (3), 630-640, 2012 | 13 | 2012 |
| A comprehensive TCAM test scheme: An optimized test algorithm considering physical layout and combining scan test with at-speed BIST design HH Wu, JN Lee, MC Chiang, PW Liu, CF Wu 2009 International Test Conference, 1-10, 2009 | 6 | 2009 |
| Rapid prototyping for digital signal processing systems using parameterized synchronous dataflow graphs HH Wu, H Kee, N Sane, W Plishker, SS Bhattacharyya Proceedings of 2010 21st IEEE International Symposium on Rapid System …, 2010 | 5 | 2010 |
| CAMEL: An efficient fault simulator with coupling fault simulation enhancement for CAMs HH Wu, JF Li, CF Wu, CW Wu 16th Asian Test Symposium (ATS 2007), 355-360, 2007 | 5 | 2007 |
| Multiple two-phase data processing with mapreduce HH Wu, TC Yeh, CM Wang 2014 IEEE 7th International Conference on Cloud Computing, 352-359, 2014 | 4 | 2014 |
| Modeling and optimization of dynamic signal processing in resource-aware sensor networks SS Bhattacharyya, W Plishker, N Sane, CC Shen, HH Wu 2011 8th IEEE International Conference on Advanced Video and Signal Based …, 2011 | 4 | 2011 |
| Generalization of large-scale data processing in one MapReduce job for coarse-grained parallelism HH Wu, CM Wang International Journal of Parallel Programming 45, 797-826, 2017 | 3 | 2017 |
| Modeling and mapping of optimized schedules for embedded signal processing systems HH Wu University of Maryland, College Park, 2013 | 3 | 2013 |
| Systematic integration of flowgraph-and module-level parallelism in implementation of DSP applications on multiprocessor systems-on-chip Z Zhou, CC Shen, W Plishker, HH Wu, SS Bhattacharyya 2012 IEEE 11th International Conference on Signal Processing 1, 402-408, 2012 | 3 | 2012 |
| Mapping parameterized dataflow graphs onto FPGA platforms HH Wu, CC Shen, H Kee, N Sane, W Plishker, SS Bhattacharyya Academic Press Library in Signal Processing 4, 643-673, 2014 | 2 | 2014 |
| Design and implementation of real-time signal processing applications on heterogeneous multiprocessor arrays HH Wu, CC Shen, SS Bhattacharyya, K Compton, M Schulte, M Wolf, ... 2010 Conference Record of the Forty Fourth Asilomar Conference on Signals …, 2010 | 1 | 2010 |
| Methods for design and implementation of dynamic signal processing systems SS Bhattacharyya 2011 International Conference on Embedded Computer Systems: Architectures …, 2011 | | 2011 |
| The Dataflow Schedule Graph and Applications to Heterogeneous Computing Systems HH Wu | | 2011 |
| Dataflow-Based Implementation of Layered Sensing Applications S Bhattacharyya, CC Shen, W Plishker, N Sane, HH Wu, R Gu, ... | | 2011 |
Shuvra S. BhattacharyyaProfessor of Electrical and Computer Engineering, University of MarylandBestätigte E-Mail-Adresse bei umd.edu
