| Arrays of single-walled carbon nanotubes with full surface coverage for high-performance electronics Q Cao, S Han, GS Tulevski, Y Zhu, DD Lu, W Haensch Nature nanotechnology 8 (3), 180-186, 2013 | 539 | 2013 |
| FinFET modeling for IC simulation and design: using the BSIM-CMG standard YS Chauhan, D Lu, S Vanugopalan, S Khandelwal, JP Duarte, ... Academic Press, 2015 | 241 | 2015 |
| BSIM-IMG: A compact model for ultrathin-body SOI MOSFETs with back-gate control S Khandelwal, YS Chauhan, DD Lu, S Venugopalan, MAU Karim, ... IEEE Transactions on Electron Devices 59 (8), 2019-2026, 2012 | 120 | 2012 |
| Modeling advanced FET technology in a compact model MV Dunga, CH Lin, X Xi, DD Lu, AM Niknejad, C Hu IEEE Transactions on Electron Devices 53 (9), 1971-1978, 2006 | 116 | 2006 |
| BSIM4v4. 7 MOSFET model TH Morshed, DD Lu, WM Yang, MV Dunga, X Xi, J He, W Liu, MC Kanyu, ... Dept Elect Eng Comput Sci Univ Calif. Berkeley Berkeley CA USA Tech Rep, 2011 | 86 | 2011 |
| Ultra-Low Power Robust 3bit/cell Hf0.5Zr0.5O2 Ferroelectric FinFET with High Endurance for Advanced Computing-In-Memory Technology S De, DD Lu, HH Le, S Mazumder, YJ Lee, WC Tseng, BH Qiu, MA Baig, ... 2021 symposium on VLSI technology, 1-2, 2021 | 76 | 2021 |
| BSIM-MG: A versatile multi-gate FET model for mixed-signal design MV Dunga, CH Lin, DD Lu, W Xiong, CR Cleavelin, P Patruno, JR Hwang, ... 2007 IEEE Symposium on VLSI Technology, 60-61, 2007 | 68 | 2007 |
| Compact modeling of variation in FinFET SRAM cells DD Lu, CH Lin, AM Niknejad, C Hu IEEE Design & Test of Computers 27 (2), 44-50, 2010 | 57 | 2010 |
| FinFET with encased air-gap spacers for high-performance and low-energy circuits AB Sachid, YM Huang, YJ Chen, CC Chen, DD Lu, MC Chen, C Hu IEEE Electron Device Letters 38 (1), 16-19, 2016 | 55 | 2016 |
| Uniform Crystal Formation and Electrical Variability Reduction in Hafnium-Oxide-Based Ferroelectric Memory by Thermal Engineering S De, BH Qiu, WX Bu, MA Baia, PJ Sung, CJ Su, YJ Lee, DD Lu ACS Applied Electronic Materials 3, 619-628, 2021 | 53 | 2021 |
| Extraction of isothermal condition and thermal network in UTBB SOI MOSFETs MA Karim, YS Chauhan, S Venugopalan, AB Sachid, DD Lu, BY Nguyen, ... IEEE Electron Device Letters 33 (9), 1306-1308, 2012 | 53 | 2012 |
| First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications SW Chang, PJ Sung, TY Chu, D Lu, CJ Wang, NC Lin, CJ Su, SH Lo, ... IEEE International Electron Devices Meeting, 254-257, 2019 | 52 | 2019 |
| Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications S De, MA Baig, BH Qiu, F Müller, HH Le, M Lederer, T Kämpfe, T Ali, ... Frontiers in Nanotechnology 3, 826232, 2022 | 47 | 2022 |
| A multi-gate MOSFET compact model featuring independent-gate operation DD Lu, MV Dunga, CH Lin, AM Niknejad, C Hu 2007 IEEE International Electron Devices Meeting, 565-568, 2007 | 46 | 2007 |
| Bsim4v4. 8.0 mosfet model N Paydavosi, TH Morshed, DD Lu, WM Yang, MV Dunga, XJ Xi, J He, ... University of California, Berkeley (CA), 2013 | 42 | 2013 |
| Number and volume raindrop size distributions in Taiwan JY Lu, CC Su, TF Lu, MM Maa Hydrological Processes: An International Journal 22 (13), 2148-2158, 2008 | 40 | 2008 |
| Read-optimized 28nm hkmg multibit fefet synapses for inference-engine applications S De, F Müller, HH Le, M Lederer, Y Raffel, T Ali, D Lu, T Kämpfe IEEE Journal of the Electron Devices Society 10, 637-641, 2022 | 39 | 2022 |
| A computationally efficient compact model for fully-depleted SOI MOSFETs with independently-controlled front-and back-gates DD Lu, MV Dunga, CH Lin, AM Niknejad, C Hu Solid-state electronics 62 (1), 31-39, 2011 | 36 | 2011 |
| Bottom oxidation through STI (BOTS)—A novel approach to fabricate dielectric isolated FinFETs on bulk substrates K Cheng, S Seo, J Faltermeier, D Lu, T Standaert, I Ok, A Khakifirooz, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 35 | 2014 |
| Robust binary neural network operation from 233 K to 398 K via gate stack and bias optimization of ferroelectric FinFET synapses S De, HH Le, BH Qiu, MA Baig, PJ Sung, CJ Su, YJ Lee, DD Lu IEEE Electron Device Letters 42 (8), 1144-1147, 2021 | 34 | 2021 |
Ali M NIKNEJADUC BerkeleyBestätigte E-Mail-Adresse bei berkeley.edu
